AMD 2901, AMD 2909 Simulator
This is a simulator for the AMD 2901, AMD2909 chips. The simulator has been created for learning purposes by a few students from 341CA class in the Automatics and Computer Science Faculty in the "POLITEHNICA" University of Bucharest.
The authors are:
| Opincaru Cristian | opincaru@yahoo.com |
| Sarbu Adrian | archi@go.ro |
| Stoicescu Radu | monicav@fx.ro |
| Viisoreanu Monica | radu_stoicescu@hotmail.com |
Thanks to Kos (Cosmin IONESCU) for the interesting suggestions ...
The project comprises a compilator for easy creation of programs, an emulator which simulates both the execution and the command unit of the AMD microprocessor, an IDE and this documentation.
Hereafter are the specifications for the command and respectively execution unit for the AMD microprocessor
AMD 2909 Command Unit
The command unit controls the execution an the flow of the program.
Short list of instructions:
|
P3:0 Code (in Hexa) |
Operation |
Name of instruction |
|
0 |
Jump to R if F !=0 |
JRNZF |
|
1 |
Jump to R |
JR |
|
2 |
Continue |
CONT |
|
3 |
Jump to D |
JD |
|
4 |
Jump to Subroutine addressed by R if F!=0 |
JSRNZF |
|
5 |
Jump to subroutine addressed by R |
JSR |
|
6 |
Return from Subroutine |
RS |
|
7 |
Jump to the adress in top of STIVA without POP action |
JSTV |
|
8 |
End cicle and POP if F==0 |
TCPOZF |
|
9 |
PUSH and CONTINUE |
PUCONT |
|
A |
POP and CONTINUE |
POCONT |
|
B |
End cicle and POP if Cn+4==1 |
TCPOP |
|
C |
Jump to R if F==0 |
JRZF |
|
D |
Jump to R if F3==1 |
JRF3 |
|
E |
Jump to R if OVR==1 |
JROVR |
|
F |
Jump to R if Cn+4==1 |
JRC |
Details
Syntax: JRNZF x
Expects: P3:0=0 //instruction code
x=target address //in decimal;
What it does: Test F. If F!=0 jumps to address X.
How it works:
If F!=0
P3:0 = 0
R = X
S1, S0 = 0, 1
!FE, PUP = 1, *
OR = 0
!ZERO = 1
Syntax: JR x
Expects: P3:0=1
x=target address
What it does: Unconditional jump to address X
How it works: P3:0 = 1
R = X
S1, S0 = 0, 1
!FE, PUP = 1, *
OR = 0
!ZERO = 1
Syntax: CONT
Expects: P3:0=2
What it does: Nothing, just continue
How it works P3:0=2
Syntax JD
Expects: P3:0=3
What it does: Jump to the address contained in DATA field
How it works: P3:0 = 1
S1, S0 = 1, 1
!FE, PUP = 1, *
OR = 0
!ZERO = 1
Syntax: JSRNZF x
Expects: P3:0=4
What it does: Execute subroutine at adress x if F!=0
How it works: if F!=0
x is forced into RR registry
P3:0 = 4
R = x
S1, S0 = 0, 1
!FE, PUP = 0, 1
OR = 0
!ZERO = 1
Syntax: JSR x
What it does: Unconditionally execute subroutine at adress x
How it works
P3:0 = 5
R = x
S1, S0 = 0, 1
!FE, PUP = 0, 1
OR = 0
!ZERO = 1
Syntax: RS
What it does: Return from Subroutine
How it works:
P3:0 = 6
S1, S0 = 1, 0
!FE, PUP = 0, 0
OR = 0
!ZERO = 1
Syntax: JSTV
What it does: Jump at the address contained in the top of the STIVA without POP
How it works
P3:0 = 7
S1, S0 = 1, 0
!FE, PUP = 1, *
OR = 0
!ZERO = 1
Syntax: TCPOZF
What it does: End cycle and POP if R==0
Syntax: PUCONT
What it does: Push and then continue
Syntax: POCONT
What it does: Pop and then continue
Syntax: TCPOC
What it does: End cycle and pop if Cn+4==1
Syntax: JRZF x
What it does: Jump to address x if F==0
Syntax: JRF3 x
What it does: Jump to adress x if F3==0
Syntax: JROVR x
What it does: Jump to address x if OVR==1
Syntax: JRC x
What it does: Jump to address x if Cn+4==1
The execution unit is responsible for resolving the arithmetico-logical operations
Registry Rx (an 'R' followed by
an integer designating the address)
Registry Q
Q
Date x(an integer)
0
Implemented microinstructions
· instruction: ADD
syntax : op1=op2+op3
effect: op1 will be the sum of op2 and op3
operand type: op1 – RAM or Q registry (destination)
op2 – RAM or Q registry, data(xH);
op3 – RAM or Q registry, data(xH);
effect (microinstruction):
Cn=0;
Source selection:
I2 I1 I0: op 2
op 3
000 RAM “A” + Q
A3A2A1A0 = op2 (Rx) Q
001 RAM “A” + RAM “B”
A3A2A1A0=op2 =Rx; B3B2B1B0=op3=Rx
101 RAM “A” + date
A3A2A1A0=op2 op3=xH
110 Q + date
Q op3=xH
(the compiler will permit only the following operation types: REG +Q, REG +REG, REG+date, Q+date and destination: REG or Q)
Operation code :
I5 I4 I3: 000 //ADD
Destination selection:
I8 I7 I6: B3 B2 B1 B0
011 op 1 //RAMF
- the result is placed in RAM in reg op1;
000 xxxx //QREG
- the result is placed in reg Q
· instruction: SUB
syntax: op1=op2-op3;
effect:
operand type: idem ADD;
effect
Cn=0;
source selection: idem ADD;
operation code
I5 I4 I3: 001 // SUB;
destination selection idem ADD;
·
instruction OR
syntax: op1=op2|op3
operand type: idem ADD;
effect
source selection: idem ADD;
operation code
I5 I4 I3 011 //OR
destination selection: idem ADD
· instruction AND
syntax: op1=op2&op3
operand types: idem ADD;
effect
source selection: idem ADD;
operation code:
I5 I4 I3 100 // AND
destination selection idem ADD
· instruction NOTRS, MASK
syntax: op1&MASK(op2)
operand type: op1 – registru RAM sau Q (Rx sau Q)
op2 – date (xH);
effect:
source
selection:
I2 I1 I0 op1
op2
101 RAM “A” date
A3A2A1A0=op1;
110 reg Q date
(the compiler will only permit the following data types : REG & data or Q & data)
operation selection:
I5 I4 I3 101 //NOTRS
destination
selection
op1 specifies the destination
I8 I7 I6: B3 B2 B1 B0
011 op 1 //RAMF
- the result is placed in RAM in at op1 address;
000 xxxx //QREG
- the result is placed in Q
· instruction EXOR
syntax: op1=op2^op3;
operand type: idem ADD
effect:
source selection idem ADD;
operation selection:
I5 I4 I3 110 //NOTRS
destination selection: idem ADD;
· instruction INC //this implementation uses Cn=1;
//it will only increment a REG (Rx) or q Q
syntax: INC op;
operand type: op- REG (Rx) sau Q;
effect
cn=1
source selection:
I2 I1 I0
0 1 1 - increments a REG (Rx), B3B2B1B0=op;
0 1 0 - increments Q
(the compiler will only accept a REG or Q to be implemented)
operation selection:
I5 I4 I3 000// ADD
destination selection: idem ADD;
op I8 I7 I6: B3 B2 B1 B0
REG(Rx) 011 op – deja setat la selectarea sursei //RAMF
-rezultatul este pus in RAM in registrul op;
Q 000 xxxx //QREG
-rezultatul este pus in reg Q
· instruction DEC
//it will only decrement a REG (Rx) or q Q
syntax: DEC op;
operand type: op – REG (Rx) sau Q;
it doe: op=op-1 by using SUB an verifying op to be REG or Q
· multiply by 2
syntax: op1=op2*2;
operand type: op1 – RAM;
op2 – RAM or Q
reads a RAM value and writes it back shifted to the left by 1 using RAMSHIFT
effect:
B3B2B1B0 = op1; - RAM address where the result will be written
source selection: 0 and (RAM or Q)
I2 I1 I0 = 010 – 0 and Q
I2 I1 I0 = 100 – 0 and A (RAM)
A3A2A1A0=op2
Operation selection // OR
I5 I4 I3 =011;
Destination selection
I8 I7 I6= 111 // shift to the left an write to RAM
· divide by 2
syntax: op1=op2*2;
operand type: op1 – RAM;
op2 – RAM or Q
reads a RAM value and writes it back shifted to the right by 1 using RAMSHIFT
effect:
B3B2B1B0 = op1; - RAM address where the result will be written
source selection: 0 and (RAM or Q)
I2 I1 I0 = 010 – 0 and Q
I2 I1 I0 = 100 – 0 and A (RAM)
A3A2A1A0=op2
Operation selection // OR
I5 I4 I3 =011;
Destination selection
I8 I7 I6= 101 // shift to right an write to RAM
· LOAD
syntax: LOAD op, val
tip op: op – reg RAM (Rx) or Q;
val – value date (x)
effect // executes OR between val and 0 ( D and 0) and puts the result in RAM at op (B3B2B1B0=op)
D3D2D1D0 = val // D=val
source selection: //D and 0
I2 I1 I0=111;
operation selection: //OR
I5 I4 I3 =011;
destination selection://RAM address op or Q;
Q: I8 I7 I6 =000 // Q<-F
RAM
B3B2B1B0 = op // where it writes
I8 I7 I6= 011 //RAMF
· instruction: READ
syntax: READ op
operand type: op – RAM(Rx) or Q
effect
the sources are (0 and B) or (0 and Q) for RAM and respectively Q; OR is executed in UAL and then NOP to destination selection
Source selection
REG (0 and B) 0 1 1 op
Q(0,Q) 0 1 0 xxxx
operation selection: //operatia este OR
I5 I4 I3 =011;
destination
selection:
I8 I7 I6 = 0 0 1 //NOP;
· instruction: NOP
syntax: NOP
effect
source selection I2 I1 I0 = 011
operation selection I5 I4 I3= 011
destination selection I8 I7 I6=001 //NOP
· instruction CLR
syntax: CLR op;
operand type: op- Registru RAM (Rx) sau Q
effect
source selection
op
I2 I1 I0 B3B2B1B0
RAM 0 1 1 op
Q 0 1 0 xxxx
operation selection - AND
I5 I4 I3 = 100;
destination selection
Op
I8 I7 I6
Registru RAM 0 1 1 //RAMF
Q 0 0 0 //QREG
· instruction ROTUP
syntax: ROTUP op
tip operand - RAM
effect
.
MUX1=0;MUX2=1;
source selection
I2 I1 I0 =011 // 0 and B
B3B2B1B0=op
operation
selection
I5 I4 I3 = 011 //OR
destination
selection
I8 I7 I6 = 111 //RAMUp
· instruction ROTDWN
syntax: ROTUP op
tip operand - RAM
effect
.
MUX1=0;MUX2=1;
source selection
I2 I1 I0 =011 // 0 and B
B3B2B1B0=op
operation
selection
I5 I4 I3 = 011 //OR
destination selection
I8 I7 I6 = 101 //RAMDown
· instruction DBLROTUP
syntax: DBLROTUP Rx, Q
effect
MUX1=1;MUX2=0;
source selection
I2 I1 I0 = 011 // 0 and B
B3B2B1B0 = Rx;
operation selection
I5 I4 I3 = 011 //OR
destination selection
I8 I7 I6 =110 // RAMQUp
· instruction DBLROTDWN
syntax: DBLROTUP Rx, Q
effect
MUX1=1;MUX2=0;
source selection
I2 I1 I0 = 011 // 0 and B
B3B2B1B0 = Rx;
operation selection
I5 I4 I3 = 011 //OR
destination selection
I8 I7 I6=100 //RAMQDown